2025-12-12T12:25:14.715 TM(5,2) ab80: SWA_E_HIS_MEM_EDAC_CORR
2025-12-12T14:28:27.980 TM(5,2) ab80: SWA_E_HIS_MEM_EDAC_CORR
2025-12-12T14:28:28.852 TM(5,2) ab8b: SWA_E_HIS_FPGA_SRAM_EDAC
2025-12-12T22:33:29.532 TM(5,2) ab80: SWA_E_HIS_MEM_EDAC_CORR
2025-12-12T22:33:30.531 TM(5,2) ab8b: SWA_E_HIS_FPGA_SRAM_EDAC
2025-12-13T10:43:29.745 TM(5,2) ab80: SWA_E_HIS_MEM_EDAC_CORR
2025-12-13T10:43:30.613 TM(5,2) ab8b: SWA_E_HIS_FPGA_SRAM_EDAC
2025-12-15T09:51:12.918 TM(5,2) aa1c: EAS1 manager: during ENG7 mode, the HK length stored in the RB does not match the expected one
2025-12-15T09:51:33.918 TM(5,2) aa1d: EAS2 manager: during ENG7 mode, the HK length stored in the RB does not match the expected one
2025-12-16T04:28:32.430 TM(5,2) ab8b: SWA_E_HIS_FPGA_SRAM_EDAC
2025-12-16T09:58:16.837 TM(5,2) ab80: SWA_E_HIS_MEM_EDAC_CORR
2025-12-17T22:08:36.080 TM(5,2) ab80: SWA_E_HIS_MEM_EDAC_CORR
2025-12-17T22:08:37.080 TM(5,2) ab8b: SWA_E_HIS_FPGA_SRAM_EDAC
2025-12-18T05:05:57.631 TM(5,2) ab80: SWA_E_HIS_MEM_EDAC_CORR